Field of the Invention
The present invention relates generally to computer systems and, more specifically, to an address bit remapping scheme to reduce access granularity of DRAM accesses.
Description of the Related Art
Current memory interfaces typically implement a data bus and a command bus for communicating with a memory device. The command bus is used to send row and column commands and addresses to the memory device, while the data bus is used to transfer read and write data to or from the memory device. For example, the JEDEC specification for DDR3 SDRAM defines sixteen address pins (A0-A15), three bank address pins (BA0-BA2), and five command pins (CS#, CKE#, RAS#, CAS#, WE#), for a total of twenty-four pins. The JEDEC specification for GDDR5 SGRAM defines fourteen address pins (A0-A12, plus RFU (Reserved)) and four bank address pins (BA0-BA3), an address bus inversion pin (ABI#), and five command pins (CS#, CKE#, RAS#, CAS#, WE#), for a total of fifteen pins.
Each command operation results in a fixed number of data transfers from the memory device. This fixed number is referred to as the minimum burst length. The burst length of a memory transaction between a memory controller and a memory device, such as a dynamic random access memory (DRAM) device, is determined by the ratio between the frequency of the memory interface between a conventional memory controller and the DRAM device and the frequency at which the DRAM device core operates. As DRAM devices have evolved over time, the second frequency has remained relatively constant, but the first frequency has generally increased with each new generation of DRAM device. For example, a double data rate (DDR) DRAM device that performs two data transfers per clock cycle, e.g., a DDR2 device, uses a minimum burst length of 4, and DDR3/sDDR3/LPDDR3/GDDR5 devices use a minimum burst length of 8. Assuming the trend continues, the next generation of DRAM devices could have a minimum burst length of 16 or higher.
As the minimum burst length increases, and with wider memory interface widths, the minimum amount of data that is transmitted over the memory interface between the DRAM device and the memory controller during a burst, referred to as “the minimum prefetch,” increases. For example, on an x64 memory interface, the minimum prefetch was 32-bytes for DDR2 devices, but the minimum prefetch increased to 64-bytes for DDR3 devices. Increased minimum prefetch causes inefficiencies for conventional memory controllers designed to access a DRAM device in 32 byte increments. Additionally, the 32 byte increments may not be stored in adjacent memory locations within the DRAM. When the amount of data that is transmitted over the memory interface between the DRAM and the processor during a burst increases from 32 bytes to 64 bytes half of the data may not be needed and is discarded by the memory controller.
One possible approach to dealing with the above problem would be to redesign conventional processors to access data in 64 byte or larger increments. As a general matter, re-designing a processor is generally undesirable for time and cost reasons. Also, on a single interface, it may be desirable for the memory controller to access different non-contiguous locations on the DRAM page. A 64-byte prefetch forces a memory controller to always access consecutive locations in a page.
Another possible approach is to add an additional interface to allow for independent access to each interface. This approach splits the 64-bit data interface into two separate data ports to provide two 32-bit data interfaces that each support accesses having a minimum burst size that is half of the minimum burst length for a single 64-bit interface. The number of pins needed to transmit and receive the data is unchanged for two 32-bit data interfaces compared with a single 64-bit data interface. However, independent command and address information is needed for each data port so that the 32 byte increments of data are not constrained to be stored in adjacent memory locations or be otherwise related in a manner that allows the same address to be used to access the two separate data ports. For these reasons, a dedicated command and address interface would usually be provided for each data interface. However, each additional dedicated command and address interface requires additional pins. Increasing the number of pins is usually undesirable because the cost of the device in area and power may also increase.
As the foregoing illustrates, what is needed in the art is an improved approach for accessing non-contiguous locations within the same memory page.